Dear Forum

My intention is to use SLG4682x as power sequencer in our newest Zynq MPSoC design.
Initial NVM programming will be done during production test through testpoints on I2C with the MPSoC unpowered.

In the product, the I2C-bus is controlled by MPSoC as master and available only after the SLG4682x controlled power sequencing. Therefore a field update becomes risky if the NVM programming is interrupted by a power fail: The sequencing will not work due to the now corrupted NVM and the mentionned testpoints are not accessible in the field.

What is your suggestion to solve this issue? Is there an AN or possibly some white paper dealing with it.

Ideal would be the possibility to boot the device from the EEPROM (e.g. by a single bit switch) until the NVM-Update had been verified as a whole and considered good. But as I understand from the datasheet, the EEPROM is just accessible over I2C and completely unrelated to the CPLD functionality. Am i Wrong?

Thanks for your inputs in advance & best regards
Peter