Hi,
I need to develop a software that allows me to have the lowest consumption in debug mode (no OTP for the moment)
At this time, I have a power consumption of about 500 µA. I have choosen CFG_DEEP_SLEEP option in my code.
我的问题是:
- Is it possilble to have the DEEP_SLEEP power consumption profil in debug mode? (500nA)
- If is it possible, what are the good options and the good manner to do that?
问候
HiGuignier,
when loading software via UART of JLINK into SysRam (debug/development mode), it's best to use extended sleep. In this mode the memory contents are retained.
In deep-sleep, they are lost, and without OTP content to copy the code from, the devices stops working after wake up from deep-sleep.
Extended-sleep current is about 1.5 µA - this value depends on the amount of reserved memory.
Best regards, BB_Dialog.