I've got an application with fairly atypical peripheral requirements, and I'd like to evaluate all of my options to reduce system power and determine if this chipset is appropriate, but I'm a little confused on a few matters regarding internal power management.
1) If I do not use the internal DC-DC converters, what are the minimum voltages for all of the different domains? (digital, RF, "retention ?") Which pins are these? I already have a few low voltage domains in my system, and they may overlap quite well to reduce power. It would also be ideal if I did not need a 3V rail, as the highest voltage in the rest of my system is actually 1.8V. If the 3V rail is only used for OTP mirroring, is it something that I could generate, for example, only once during startup, and not require it after boot?
2) If I do use the internal boost converter, what types of output voltages and currents can I expect to be able to power off of the outputs? I understand there are two outputs to the boost converter - a VBAT3V (3V nominal), and VDCDC (1.4V nominal). VBAT3V falls to VDCDC voltages during sleep, while VDCDC is always on at 1.4V, correct? Are any of these voltages adjustable?
3) How much current can they source for an external application? Unlike previous answers I've seen, my peripherals use at most 10s of microamps, so they are not large loads at all - is it possible to still power these while the device is in sleep?
4) Same scenario as #3, except in buck converter - could I use some current from the 1.4V output on VDCDC?
5) What is the GPIO voltage in all of the scenarios? Is this controlled via software, or does one of the pins defined above define the GPIO voltages?
Also, a side question - I've noticed that there's a new DA14680 chipset. Are there any improvements in terms of power management I might expect with that chipset, or are there only feature improvements?
Thanks!
Samson
Hi samsonc,
1) If you would like to bypass the internal DCDC converter you can follow the FAQhttps://support.dialog-semiconductor.com/guide/faq-hardware-peripherals"Is it possible to bypass the internal DCDC converter", stating the exact voltage of the internal components of the 580 (RF, Digital, etc) i dont think that makes sense since you wont be able to access them and supply them separatelly, regarding the available pins, you can check that in the datasheet which pins are available on the 580 package. I dont get the question regarding the 3V, this is the standard output of the DCDC when operating in Boost mode, and the 3V are used not only during OTP read, ommiting this rail is not going to be a viable solution.
2) The internal DCDC is designed to power only the 580 and not extrernal devices, therefore the amount of current and what kind of loads can be connected has not been characterized. When the 580 falls to sleep and the boost converter is off, the VBAT3V has a value of VBAT1 or slightly less. You mean if can configure the internal DCDC to produce a different range of values ? No that is not possible.
3) As previously mentioned supplying external components has not been characterized, and also the DCDC converter is powered off when the device goes to sleep.
4) Again, the DCDC is designed to supply only the 580 and not external loads.
5)关于GPIOs其上的电压VBAT3V when the device operates in buck mode, and there is no option for that, and there is an option when the device operates under Boost mode, you can choose between the VBAT3V and the VBAT1V rail.
Regarding the 68x family, its tottaly different SoC with a tottaly different power management component, please check the datasheet for more info on this.
Thanks MT_dialog