How to configure XIP from QSPI with CODE_SIZE greater than 512KB | Dialog Semiconductor customer support

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Mon, 2019-05-20 15:58

Garry Clarkson

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How to configure XIP from QSPI with CODE_SIZE greater than 512KB

Hi Team,

I have a DA1469x ProKit and building code with SDK_10.0.4.66 and this has a standard MX25U3235F flash device. I am performing an evaluation to check the device will meet the requirements for a customer application.

My application is configured to execute as XIP from QSPI and the initial test using sample application freertos_retarget builds and runs fine when using the 4MB partition table.

Now when I am adding the rest of my application I have linked in some proprietary code libraries and constant code tables which increases the code mapped to the ROM region to larger than the default 512KB. The ROM linker region grows to around 800KB. I have left the cache for QSPI configured as default at 64KB.

I have created a modified 4M based partition table which defines the firmware partition to be larger as per below and I have adjusted the linker scripts:

#define NVMS_PRODUCT_HEADER_PART_START 0x000000 #define NVMS_PRODUCT_HEADER_PART_SIZE 0x002000 #define NVMS_FIRMWARE_PART_START 0x002000 /* Alignment to 512KB is dictated by the default FLASH_REGION_SIZE. */ #define NVMS_FIRMWARE_PART_SIZE 0x0DE000 /* Increased from default 0x07E000 to use empty space */

I flashed the device using theprogram_qspi_jtagscript which appears to flash all the sectors correctly however I am unable to read back any constant data or execute code from addresses above 0x80000 (remapped) or 0x36080000 direct. Is it even possible to have aNVMS_FIRMWARE_PART_SIZEgreater than 512KB?

Either theprogram_qspi_jtagscript is failing to flash the upper regions correctly or the QSPI memory (re)mapping is somehow still misconfigured.

Please can you offer any guidance.

Thanks

~Garry

Device:

DA1469x

Tue, 2019-05-21 17:29

PM_Dialog

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Hi Garry Clarkson,

Please check the Table 976 of DA1469x datasheet. By default, the FLASH region size is set at 0.5 Mbytes, but this value can be changed by programming the CACHE_FLASH_REG[FLASH_REGION_SIZE] in the OTP header. The CACHE_FLASH_REG[FLASH_REGION_BASE] and CACHE_FLASH_REG[FLASH_REGION_OFFSET] will be set by the bootloader, so you don’t need to program them. ONLY CACHE_FLASH_REG[FLASH_REGION_SIZE] must be programmed.

假设你想to have 1MB FLASH region size, so you will have to set the CACHE_FLASH_REG[FLASH_REGION_SIZE] to 0x5. Please find attached the steps you should follow in order to program the OTP header.
燃烧的OTP头后,应该改变the partition table, because the FW partitions must be aligned to 1MB with offset up to 0x4000. In general the FW partition must be aligned to FLASH_REGION_SIZE. You could find a reference partition table in the attachments. As you can see, both firmware and generic partition are 1MB aligned. The NVMS_PRODUCT_HEADER should start at 0x0000 and the size should be 0x2000. Except from the NVMS_PRODUCT_HEADER, NVMS_FIRMWARE and NVMS_GENERIC_PART could be modified according your implementation and requirements. Make sure that you have set the correct value according to Table 976 and burn the OTP header.
In case you use the MX25U3235F and 4MB partition table, you must have the same configurations as in config.png snapshot. Run the program_qspi_config script in order to make sure that you have the same configurations. Unless, please change them.
First Erase and then program the QSPI by executing the appropriate scripts. After that open the QSPI Partition Table form the Tools bar of SmartSnippets toolbox. It is strongly recommended to use the latest version of the tool which is version 2.0.8. If you press connect and read, you will see the updated partition table as in partition_table.PNG snapshot. The NVMS_PARTITION_TABLE should start at QSPI address 0x3FF00 and 4 kBytes (1 FLASH sector size) should be placed before the end of the selected FLASH size. If this is not the case, then Toolbox will not recognize your new partition scheme (NVMS_PARTITION_TABLE.PNG)!

In addition, if you would like to have SUOTA functionality, the SUOTA partition table must be modified respectively.

Thanks, PM_Dialog

Attachment:

attachments.zip

星期四,2019-05-23 34

Garry Clarkson

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Last seen:1 year 11 months ago

Joined:2019-04-16 09:57

Hi,

many thanks for the guidance and step by step instructions. I was setting CACHE_FLASH_REG[FLASH_REGION_SIZE] to 0x5 early in the startup code without realising this must be done via the OTP route.

I instead changed to use a 2Mbyte configuration by setting CACHE_FLASH_REG[FLASH_REGION_SIZE] to 0x4 for some headroom and adjusted the partition table. It is now working fine. Thanks for your help.

Regards,

Garry

Thu, 2019-05-23 10:53

PM_Dialog

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Hi Garry,

Glad that you figured your issue out. If you found my answer useful, please mark it as “accepted”.

Thanks, PM_Dialog

Thu, 2019-05-23 11:14

PM_Dialog

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Hi Gary,

In addition you should change the dg_configQSPI_CODE_SIZE_AA macro in bsp_memory_defaults.h file. Please make the following modifications in bsp_memory_defaults.h

#ifndef dg_configQSPI_MAX_IMAGE_SIZE #define dg_configQSPI_MAX_IMAGE_SIZE ( IMAGE_PARTITION_SIZE ) #endif #ifndef dg_configQSPI_CODE_SIZE_AA #define dg_configQSPI_CODE_SIZE_AA (dg_configQSPI_MAX_IMAGE_SIZE - (136*1024)) /* Take into account CMI firmware size */ #endif

The 136KB is the size of the CMAC which is running in M0+.

Thanks, PM_Dialog