水晶装饰和lld_sleep_compensate_func警告

你好，

1.我使用RCX，没有使用外部LP晶体。

2。I have not. I have made two modifications to the SDK:

1. to retrieve the BLE address easily I extern'd struct bd_addr app_random_addr

2.如果不存在，我修改了Arch_System以从Config标志而不是OTP检索默认的Cryst Carrim值，如下所示：

#if定义（__da14531__）+＃ifdef cfg_default_xtal32m_trim_value ^ m +＃define default_xtal32m_trim_value_qfn（cfg_default_xtal32m_trim_value）+＃define default_xtal32m_trim_value_wlcsp（cfg_default_xtal32m_trim_value）+＃else

CFG_DEFAULT_XTAL32M_TRIM_VALUE is 0x80 for the QFN chip by default, which does not cause the warning, but at 0xFF it does.

3. I do not believe I ever disable interrupts. I have reviewed my code and have found no direct, or indirect through dialog API calls, way in which I disable them.

4. I have checked periph_init. The only calls it makes are to GPIO_ConfigurePin (lights_init() also just calls GPIO_ConfigurePin())

空白set_pad_functions(空白)/ /设置gpio端口function mode { GPIO_ConfigurePin(CLIP_SWITCH_PORT, CLIP_SWITCH_PIN, INPUT, PID_GPIO, false); GPIO_ConfigurePin(CLIP_TEMP_SENSOR_EN_PORT, CLIP_TEMP_SENSOR_EN_PIN, OUTPUT, PID_GPIO, false); GPIO_ConfigurePin(CLIP_TEMP_SENSOR_PORT, CLIP_TEMP_SENSOR_PIN, INPUT, PID_ADC, false); } void periph_init(void) // set i2c, spi, uart, uart2 serial clks { #if defined (__DA14531__) // Disable HW Reset functionality of P0_0 GPIO_Disable_HW_Reset(); // In Boost mode enable the DCDC converter to supply VBAT_HIGH for the used GPIOs syscntl_dcdc_turn_on_in_boost(SYSCNTL_DCDC_LEVEL_3V0); #else // Power up peripherals' power domain SetBits16(PMU_CTRL_REG, PERIPH_SLEEP, 0); while (!(GetWord16(SYS_STAT_REG) & PER_IS_UP)); SetBits16(CLK_16M_REG, XTAL16_BIAS_SH_ENABLE, 1); #endif // ROM patch patch_func(); // Set pad functionality set_pad_functions(); lights_init(); // Enable the pads GPIO_set_pad_latch_en(true); }

我正在使用自定义代码。固件处于延迟测试版或发布候选阶段，只有最近的批次批次，即晶体调整经历了此警告。如果我有时间，我还没有尝试运行示例代码我会调查这个问题。

如果我不能轻易解决这个问题，似乎只要我的最终调谐值保持在大约75kHz内的初始频率偏移误差，而无需修剪晶体即可导致此警告即可，我应该良好的生产。MAX BLE错误按照规格为150kHz，这应该给我充足的余量，+/- 10ppm初始，+/- 10ppm温度，以及晶体上的一些老化容差。如果这是大约30ppm的总数最坏情况，则可以在产品的预期寿命中获得〜75khz的额外误差。

Thanks,

麦克风

I'm posting an update for other people experiencing the same problem. I diagnosed it to a bad crystal: the latest production test batch was actually not using XRCGB32M000F1H00R0 like the earlier batches, and some alternative crystal was substituted with unknown characteristics.

Using a calibrated frequency counter, I was able to show that it was off by 52ppm at 25C, and likely worse at other temperatures. This exactly matched the error I was seeing with my spectrum analyzer (2.402GHz * 52ppm ~=125KHz error). It may also have had the wrong capacitance, etc. My issues were resolved when I soldered the correct part in its place.

到目前为止，我无法在0x80的默认修剪中使用正确的水晶来重现此问题。如果该更改，我会更新此线程，但否则我认为此问题已关闭。