SPI master clock setup

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Thank you for your quick answer.
我在我的代码中检查并使用SPI示例。我使用AD SW层代码的所有其他部分。
I tried to decrease the SPI clock in an original way. It means change .xtal_freq value in the maximal divider enum (HW_SPI_FREQ_DIV_14)as you mentioned.
当我测量SPI SCLK信号频率时，我看到大约2.5 MHz。（我的USB示波器精度不那么高，但我相信它超过1MHz）

I am a bit confused because I checked the clock tree (page 168) and as I see this divider is the one way to decrease the SCLK frequency because the input of the divider can come from sysclk or divN clock source. divN is a fix value as I know or there isn't any interface function which I would be able to modify this value.
它的意思是for me that it is impossible to go bellow 1MHz with SCLK if I would like to use 32MHz crystal or PLL. I am sure that I miss out on something just I don't know what.

Thanks in advance

亲爱的支持

Thanks for your reply.

我切换回XTAL 32 MHz时钟，以修改AHB和APB总线分频器，并测量SCLK频率，但我无法达到任何正面结果。我尝试了几个分频器参数，但它们对SPI时钟频率没有任何影响。

在时钟树和数据表中，我看到这些分隔符只有QSPI外设影响，但它用于闪存或RAM处理。

I see approximately 2.3-2.5MHz in SPI CLK pin and one way how I can modify this frequency by the SPI clock divider as you also mentioned in the past.

Do you have any other idea how can I achieve a smaller frequency than 1MHz or we may declare that it is not possible with this architecture?

Thanks in advance

亲爱的支持
谢谢你的详细答案。我检查了这个解决方法。它的意思是
1. Set HCLK and PCLK divider
cm_sys_clk_init（sysclk_xtal32m）;
cm_apb_set_clock_divider（apb_div4）;
cm_ahb_set_clock_divider(ahb_div4);
cm_lp_clk_init();
2.修改hw_spi_init_clk_reg（）函数（我使用spi1）
void hw_spi_init_clk_reg(HW_SPI_ID id)
{
assert_warning（reg_getf（crg_top，pmu_ctrl_reg，com_sleep）== 0）;
if (id == HW_SPI1) {
CRG_COM->RESET_CLK_COM_REG = CRG_COM_RESET_CLK_COM_REG_SPI_CLK_SEL_Msk;
CRG_COM-> SET_CLK_COM_REG =（CRG_COM_SET_CLK_COM_REG_SPI_ENABLE_MSK | CRG_COM_SET_CLK_COM_REG_SPI_PLK_SEL_SEL_SEL_SEL_MSK）;
} 别的 {
crg_com-> reset_clk_com_reg = crg_com_reset_clk_com_reg_spi2_clk_sel_msk;
CRG_COM - > SET_CLK_COM_REG = CRG_COM_SET_CLK_COM_REG_SPI2_ENABLE_Msk;
}
}
3.划分SPI时钟（带14 - > 500K SCLK）
/ *外部传感器/模块SPI驱动程序* /
const ad_spi_driver_conf_t drv_SPI1_adis = {
.spi = {
.cs_pad = {device_cs_gpio_port，device_cs_gpio_pin}，
。word_mode = HW_SPI_WORD_8BIT, // Here you can define the required
.smn_role = hw_spi_mode_master，
。polarity_mode = HW_SPI_POL_LOW, // Here you can define the required SPI polarity
。phase_mode = HW_SPI_PHA_MODE_0, // Here you can define the required SPI phase
。mint_mode = HW_SPI_MINT_DISABLE,
。xtal_freq = HW_SPI_FREQ_DIV_14,
。fifo_mode = HW_SPI_FIFO_RX_TX,
。disabled = 0, /* Should be disabled during initialization phase */
.ignore_cs = false，
。use_dma = true,
。rx_dma_channel = HW_DMA_CHANNEL_2,
。tx_dma_channel = HW_DMA_CHANNEL_4
}
};

不幸的是，结果是一样的。

I checked again the datasheet but not clear for me why did you write that ,,The green line is the system clock divided by 1, 2. 4 or 8". The green line is the system clock. The ahb and apb bus clock are the system clock divided by 1,2,4,8 . The green line comes from sys_clk selector and comes directly from XTAL32, RC32, PLL , LP clock. I can modify ahb and apb bus clock but as I see the SPI periphery clock is independent from ahb or apb bus clock. (Figure 84: SPI Block Diagram) . These buses only take part in data movement.

Thanks in advance

亲爱的支持

Thank you for check this issue on your side.

Of course, I would like to make high precision IMU measurement with an ADIS16460 and send out measurements via Bluetooth.
This is the datasheet of ADIS sensorhttps://www.analog.com/en/亚博电竞菠菜products/adis16460.html.
In the datasheet, you can see the maximal SPI clock frequency on the top of page 5.

(I think after this post we may ask some money from Analog Devices, as advertise cost :) )

Thanks in advance

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