SPI master clock setup

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herangli
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SPI master clock setup

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我有一个DA14695 USB eval板,我想将设备集成到SPI上。
This slave device requires a maximum 1MHz SCLK frequency to be able to communicate.
I tried to find some solution to set a lower frequency but I haven't found any way.

Is it possible to set a lower SPI Master SCLK frequency? If it is possible please help me how.

Thanks in advance

Device:
PM_DIALOG.
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Hi herangli,

Hi herangli,

谢谢你的问题。请参阅数据表第33节和表表345:SPI_CTRL_REG。SPI_CTRL_REG [SPI_CLK]位域负责主模式下的时钟输出频率。因此,在SPI配置结构(ad_spi_driver_conf_t)中,您应该选择相应的时钟。

我建议首先检查DA1469X教程SPI适配器概念。在该教程中,选择.xtal_freq = hw_spi_freq_div_8,因此您可以根据您的要求更改它。

Generally, we strongly recommend the usage of the adapters for accessing hardware peripherals because not only provide access to the peripheral, but also make sure that other tasks which are currently accessing it, suspend their operation until the peripheral is once again released. So you don't have to worry if another task tries accessing the same peripheral at the same time. Also, in sleep mode all the peripheral blocks are powered down.

谢谢,PM_DIALOG.

herangli
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Thank you for your quick answer.
我在我的代码中检查并使用SPI示例。我使用AD SW层代码的所有其他部分。
I tried to decrease the SPI clock in an original way. It means change .xtal_freq value in the maximal divider enum (HW_SPI_FREQ_DIV_14)as you mentioned.
当我测量SPI SCLK信号频率时,我看到大约2.5 MHz。(我的USB示波器精度不那么高,但我相信它超过1MHz)

I am a bit confused because I checked the clock tree (page 168) and as I see this divider is the one way to decrease the SCLK frequency because the input of the divider can come from sysclk or divN clock source. divN is a fix value as I know or there isn't any interface function which I would be able to modify this value.
它的意思是for me that it is impossible to go bellow 1MHz with SCLK if I would like to use 32MHz crystal or PLL. I am sure that I miss out on something just I don't know what.

Thanks in advance

PM_DIALOG.
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Hi herangli,

Hi herangli,

请尝试更改分隔符:

cm_apb_set_clock_divider(apb_div1);

cm_ahb_set_clock_divider(ahb_div1);

但是,您无法将时钟装入PLL,因此系统将使用32MHz运行。请检查hw_clk_set_sysclk()函数。

谢谢,PM_DIALOG.

herangli
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Thanks for your reply.

我切换回XTAL 32 MHz时钟,以修改AHB和APB总线分频器,并测量SCLK频率,但我无法达到任何正面结果。我尝试了几个分频器参数,但它们对SPI时钟频率没有任何影响。

在时钟树和数据表中,我看到这些分隔符只有QSPI外设影响,但它用于闪存或RAM处理。

I see approximately 2.3-2.5MHz in SPI CLK pin and one way how I can modify this frequency by the SPI clock divider as you also mentioned in the past.

Do you have any other idea how can I achieve a smaller frequency than 1MHz or we may declare that it is not possible with this architecture?

Thanks in advance

PM_DIALOG.
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Hi herangli,

Hi herangli,

请查看图34:数据表中的时钟树图。所有外围块都是从系统时钟div1(绿线)或divn_clk(红线)馈送。绿线是系统时钟除以1,2。4或8。默认情况下,系统时钟分为1,位于32MHz:

cm_sys_clk_init(sysclk_xtal32m);

cm_apb_set_clock_divider(apb_div1);

cm_ahb_set_clock_divider(ahb_div1);

红线是DIVN HW块的输出,无论上述划分,频率始终为32MHz。

CLK_COM_REG处理“绿色”和“红色”线之间的选择。低级驱动程序(LLD)用32MHz时钟(红线)Divn_Clk实现。时钟频率可以进一步划分在外围HW块中(如果可能)。

专为SPI外围块,SPI控制器最多32 MHz的时钟速度,SPI源时钟可以除以2,4,8,14(根据数据表)。因此最小SPI时钟为32MHz / 14。

如果您要进一步降低SPI时钟,则应为外围时钟选择DIV1,然后将DIV1降低系统时钟以便能够获得较低的外围频率。这不建议使用,因为整体CPU性能将较低。另外,在将应用程序中触发的事件的情况下,更高频率对系统时钟的变化,例如需要PLL96的USB中的插头,这将导致外围设备中速度的无条件变化。您必须在您的应用程序中进行额外的照顾,因此在使用DIVN的外围设备的交易中将绝对不会发生系统时钟。

如果您仍需要使用1MHz SPI时钟,则可能的解决方法可能如下:

  1. Divide the System Clock by 4 in the main() function as follow

cm_sys_clk_init(sysclk_xtal32m);

cm_apb_set_clock_divider(apb_div4);

cm_ahb_set_clock_divider(ahb_div4);

The new System Clock will be 32MHz / 4 = 8MHz

  1. 相应地更改HW_SPI_INIT_CLK_REG(),然后选择DIV1时钟 - CLK_COM_REG [SPI_CLK_SEL] = 0x01
  2. Divide further the SPI clock by 8 - SPI_CTRL_REG[SPI_CLK] = 0x00 . The result will be 8MHz / 8 = 1MHz

谢谢,PM_DIALOG.

herangli
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谢谢你的详细答案。我检查了这个解决方法。它的意思是
1. Set HCLK and PCLK divider
cm_sys_clk_init(sysclk_xtal32m);
cm_apb_set_clock_divider(apb_div4);
cm_ahb_set_clock_divider(ahb_div4);
cm_lp_clk_init();
2.修改hw_spi_init_clk_reg()函数(我使用spi1)
void hw_spi_init_clk_reg(HW_SPI_ID id)
{
assert_warning(reg_getf(crg_top,pmu_ctrl_reg,com_sleep)== 0);
if (id == HW_SPI1) {
CRG_COM->RESET_CLK_COM_REG = CRG_COM_RESET_CLK_COM_REG_SPI_CLK_SEL_Msk;
CRG_COM-> SET_CLK_COM_REG =(CRG_COM_SET_CLK_COM_REG_SPI_ENABLE_MSK | CRG_COM_SET_CLK_COM_REG_SPI_PLK_SEL_SEL_SEL_SEL_MSK);
} 别的 {
crg_com-> reset_clk_com_reg = crg_com_reset_clk_com_reg_spi2_clk_sel_msk;
CRG_COM - > SET_CLK_COM_REG = CRG_COM_SET_CLK_COM_REG_SPI2_ENABLE_Msk;
}
}
3.划分SPI时钟(带14 - > 500K SCLK)
/ *外部传感器/模块SPI驱动程序* /
const ad_spi_driver_conf_t drv_SPI1_adis = {
.spi = {
.cs_pad = {device_cs_gpio_port,device_cs_gpio_pin},
。word_mode = HW_SPI_WORD_8BIT, // Here you can define the required
.smn_role = hw_spi_mode_master,
。polarity_mode = HW_SPI_POL_LOW, // Here you can define the required SPI polarity
。phase_mode = HW_SPI_PHA_MODE_0, // Here you can define the required SPI phase
。mint_mode = HW_SPI_MINT_DISABLE,
。xtal_freq = HW_SPI_FREQ_DIV_14,
。fifo_mode = HW_SPI_FIFO_RX_TX,
。disabled = 0, /* Should be disabled during initialization phase */
.ignore_cs = false,
。use_dma = true,
。rx_dma_channel = HW_DMA_CHANNEL_2,
。tx_dma_channel = HW_DMA_CHANNEL_4
}
};

不幸的是,结果是一样的。

I checked again the datasheet but not clear for me why did you write that ,,The green line is the system clock divided by 1, 2. 4 or 8". The green line is the system clock. The ahb and apb bus clock are the system clock divided by 1,2,4,8 . The green line comes from sys_clk selector and comes directly from XTAL32, RC32, PLL , LP clock. I can modify ahb and apb bus clock but as I see the SPI periphery clock is independent from ahb or apb bus clock. (Figure 84: SPI Block Diagram) . These buses only take part in data movement.

Thanks in advance

PM_DIALOG.
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Hi herangli,

Hi herangli,

我的意思是,如果AHB和APB总线时钟划分,则系统时钟也将分为1,2,4,8。请让我在我身边检查它,我会告诉你。

Can I ask what is the SPI interface that you are using and required SPI clack speed less than 1MHz ?

Thanks PM_Dialog

herangli
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Thank you for check this issue on your side.

Of course, I would like to make high precision IMU measurement with an ADIS16460 and send out measurements via Bluetooth.
This is the datasheet of ADIS sensorhttps://www.analog.com/en/亚博电竞菠菜products/adis16460.html.
In the datasheet, you can see the maximal SPI clock frequency on the top of page 5.

(I think after this post we may ask some money from Analog Devices, as advertise cost :) )

Thanks in advance

herangli
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您是否有机会在评估板中查看此问题?

Thank you in advance

herangli
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您是否有机会在评估板中查看此问题?

Thank you in advance

PM_DIALOG.
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Hi herangli,

Hi herangli,

谢谢你提醒,我对迟到的回应道歉。我会再试一次。

谢谢,PM_DIALOG.

PM_DIALOG.
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Hi herangli,

Hi herangli,

是否有可能在此处附上您的项目来看看?

谢谢,PM_DIALOG.