SPI master clock setup

Dear support

Thank you for your quick answer.
I checked and used the SPI example in my code. I use ad sw layer all other parts of code.
I tried to decrease the SPI clock in an original way. It means change .xtal_freq value in the maximal divider enum (HW_SPI_FREQ_DIV_14)as you mentioned.
When I measure SPI SCLK signal frequency I see approximately 2.5 MHz. (My USB oscilloscope accuracy not so high but I am sure it is over than 1MHz)

I am a bit confused because I checked the clock tree (page 168) and as I see this divider is the one way to decrease the SCLK frequency because the input of the divider can come from sysclk or divN clock source. divN is a fix value as I know or there isn't any interface function which I would be able to modify this value.
It means for me that it is impossible to go bellow 1MHz with SCLK if I would like to use 32MHz crystal or PLL. I am sure that I miss out on something just I don't know what.

Thanks in advance

Dear support

Thanks for your reply.

I switched back to xtal 32 MHz clock in order to modify ahb and apb bus clock divider and I measured SCLK frequency but I couldn't achieve any positive result. I tried several divider parameters but they didn't have any effect for SPI clock frequency.

In the clock tree and datasheet, I saw that these dividers have impact only QSPI peripherals but it is used for flash or ram handling.

I see approximately 2.3-2.5MHz in SPI CLK pin and one way how I can modify this frequency by the SPI clock divider as you also mentioned in the past.

Do you have any other idea how can I achieve a smaller frequency than 1MHz or we may declare that it is not possible with this architecture?

Thanks in advance

Dear support
Thank you for your detailed answer. I checked this workaround. It means
1. Set HCLK and PCLK divider
cm_sys_clk_init(sysclk_XTAL32M);
cm_apb_set_clock_divider(apb_div4);
cm_ahb_set_clock_divider(ahb_div4);
cm_lp_clk_init();
2. Modify hw_spi_init_clk_reg() function (I use SPI1)
void hw_spi_init_clk_reg(HW_SPI_ID id)
{
ASSERT_WARNING(REG_GETF(CRG_TOP, PMU_CTRL_REG, COM_SLEEP) == 0);
if (id == HW_SPI1) {
CRG_COM->RESET_CLK_COM_REG = CRG_COM_RESET_CLK_COM_REG_SPI_CLK_SEL_Msk;
CRG_COM->SET_CLK_COM_REG = (CRG_COM_SET_CLK_COM_REG_SPI_ENABLE_Msk |CRG_COM_SET_CLK_COM_REG_SPI_CLK_SEL_Msk);
} else {
CRG_COM->RESET_CLK_COM_REG = CRG_COM_RESET_CLK_COM_REG_SPI2_CLK_SEL_Msk;
CRG_COM->SET_CLK_COM_REG = CRG_COM_SET_CLK_COM_REG_SPI2_ENABLE_Msk;
}
}
3. divide SPI clock (with 14 -> 500k SCLK)
/* External sensor/module SPI driver */
const ad_spi_driver_conf_t drv_SPI1_adis = {
.spi = {
.cs_pad = {DEVICE_CS_GPIO_PORT, DEVICE_CS_GPIO_PIN},
.word_mode = HW_SPI_WORD_8BIT, // Here you can define the required
.smn_role = HW_SPI_MODE_MASTER,
.polarity_mode = HW_SPI_POL_LOW, // Here you can define the required SPI polarity
.phase_mode = HW_SPI_PHA_MODE_0, // Here you can define the required SPI phase
.mint_mode = HW_SPI_MINT_DISABLE,
.xtal_freq = HW_SPI_FREQ_DIV_14,
.fifo_mode = HW_SPI_FIFO_RX_TX,
.disabled = 0, /* Should be disabled during initialization phase */
.ignore_cs = false,
.use_dma = true,
.rx_dma_channel = HW_DMA_CHANNEL_2,
.tx_dma_channel = HW_DMA_CHANNEL_4
}
};

The result is unfortunately the same.

I checked again the datasheet but not clear for me why did you write that ,,The green line is the system clock divided by 1, 2. 4 or 8". The green line is the system clock. The ahb and apb bus clock are the system clock divided by 1,2,4,8 . The green line comes from sys_clk selector and comes directly from XTAL32, RC32, PLL , LP clock. I can modify ahb and apb bus clock but as I see the SPI periphery clock is independent from ahb or apb bus clock. (Figure 84: SPI Block Diagram) . These buses only take part in data movement.

Thanks in advance

Dear support

Thank you for check this issue on your side.

Of course, I would like to make high precision IMU measurement with an ADIS16460 and send out measurements via Bluetooth.
This is the datasheet of ADIS sensorhttps://www.analog.com/en/products/adis16460.html
In the datasheet, you can see the maximal SPI clock frequency on the top of page 5.

(I think after this post we may ask some money from Analog Devices, as advertise cost :) )

Thanks in advance

Dear support

Did you have a chance to check this issue in an eval board?

Thank you in advance

Dear support

Did you have a chance to check this issue in an eval board?

Thank you in advance