Thanks for your question. Please see datasheet section 33 and table Table 345: SPI_CTRL_REG. The SPI_CTRL_REG[SPI_CLK] bitfield is responsible for clock output frequency in master mode. So, in the SPI configuration structure (ad_spi_driver_conf_t), you should select the appropriate clock.
I would recommend first checking theDA1469x Tutorial SPI Adapter Concepts. In that tutorial the .xtal_freq = HW_SPI_FREQ_DIV_8 is selected, so you can change it according to your requirements.
谢谢你迅速回应。 I checked and used the SPI example in my code. I use ad sw layer all other parts of code. 我试图以原始方式减少SPI时钟。如上所述，它意味着最大分配枚举中的更改.xtal_freq值（hw_spi_freq_div_14）。 When I measure SPI SCLK signal frequency I see approximately 2.5 MHz. (My USB oscilloscope accuracy not so high but I am sure it is over than 1MHz)
Please take a look at Figure 34: Clock Tree Diagram in the datasheet. All the peripheral blocks are fed either from the system clock div1( green line ) or from divN_clk (red line). The green line is the system clock divided by 1, 2. 4 or 8. By default the system clock is divided by 1 and is at 32MHz :
cm_sys_clk_init(sysclk_XTAL32M);
cm_apb_set_clock_divider（apb_div1）;
cm_ahb_set_clock_divider(ahb_div1);
The red line is the output of the DivN HW block, and the frequency is always at 32Mhz regardless the aforementioned division.
The CLK_COM_REG handles the selection between the “green” and “red” line. The Low Level Drivers (LLD) are implemented with the 32MHz clock (red line) divN_clk. The clock frequency can be divided in the peripheral HW blocks further ( if it is possible).
Specifically for the SPI peripheral block, the clock speeds up to 32 MHz for the SPI controller and the SPI source clock can be divided by 2, 4, 8, 14 (according to datasheet). So the minimum SPI clock is at 32MHz / 14.
In case you want to lower down the SPI clock further, you should select the div1 for the peripheral clock and then lower down the System Clock to be able to get lower peripheral frequencies. This is not recommended, as the overall CPU performance will be lower. Additionally, in case of an event which will trigger in your app the change of a higher frequency to the system clock, for example plug in of the USB which require the PLL96, this will result to an unconditional change of the speed in your peripheral. You will have to take extra care in your application, so there will be absolutely no system clock changes during the transaction of your peripheral while using the divN.
If you still need to use 1MHz SPI clock, a possible workaround might be the following :
将系统时钟划分为4在main（）函数中如下
cm_sys_clk_init(sysclk_XTAL32M);
cm_apb_set_clock_divider(apb_div4);
cm_ahb_set_clock_divider（ahb_div4）;
新系统时钟将是32MHz / 4 = 8MHz
Change the hw_spi_init_clk_reg() accordingly and select the Div1 clock - CLK_COM_REG[SPI_CLK_SEL] = 0x01
I meant that if the ahb and apb bus clocks are divided, then the system clock is divided by 1,2,4,8 too. Please let me check it in my side and I’ll let you know.
嗨Herangli，
Thanks for your question. Please see datasheet section 33 and table Table 345: SPI_CTRL_REG. The SPI_CTRL_REG[SPI_CLK] bitfield is responsible for clock output frequency in master mode. So, in the SPI configuration structure (ad_spi_driver_conf_t), you should select the appropriate clock.
I would recommend first checking theDA1469x Tutorial SPI Adapter Concepts. In that tutorial the .xtal_freq = HW_SPI_FREQ_DIV_8 is selected, so you can change it according to your requirements.
通常，我们强烈建议使用适配器来访问硬件外围设备，因为不仅提供对外设的访问，而且还确保当前正在访问的其他任务，暂停其操作，直到外围设备再次释放。因此，如果另一个任务在同一时间访问相同的外围设备，则不必担心。此外，在睡眠模式下，所有外围块都断电。
Thanks, PM_Dialog
Dear support
谢谢你迅速回应。
I checked and used the SPI example in my code. I use ad sw layer all other parts of code.
我试图以原始方式减少SPI时钟。如上所述，它意味着最大分配枚举中的更改.xtal_freq值（hw_spi_freq_div_14）。
When I measure SPI SCLK signal frequency I see approximately 2.5 MHz. (My USB oscilloscope accuracy not so high but I am sure it is over than 1MHz)
我有点困惑，因为我检查了时钟树（第168页），因为我看到这个分频器是减少SCLK频率的一种方法，因为分频器的输入可以来自SYSCLK或DIVN时钟源。DIVN是我知道的修复值，或者没有任何接口功能，我能够修改此值。
这意味着我对我来说，如果我想使用32MHz水晶或PLL，那就不可能使用SCLK。我相信我错过了我不知道什么。
提前致谢
嗨Herangli，
Please try to change the dividers :
cm_apb_set_clock_divider（apb_div1）;
cm_ahb_set_clock_divider(ahb_div1);
However, you will not able to clock the clock to PLL so the system will run with the 32MHz. Please check hw_clk_set_sysclk() function.
Thanks, PM_Dialog
Dear support
感谢您的回复。
我切换回XTAL 32 MHz时钟，以修改AHB和APB总线分频器，并测量SCLK频率，但我无法达到任何正面结果。我尝试了几个分频器参数，但它们对SPI时钟频率没有任何影响。
In the clock tree and datasheet, I saw that these dividers have impact only QSPI peripherals but it is used for flash or ram handling.
我在SPI CLK引脚中看到大约2.3-2.5MHz，以及如何通过SPI时钟分频器修改此频率的一种方式。
您还有其他想法如何达到比1MHz更小的频率，或者我们可能会声明这架构不可能？
提前致谢
嗨Herangli，
Please take a look at Figure 34: Clock Tree Diagram in the datasheet. All the peripheral blocks are fed either from the system clock div1( green line ) or from divN_clk (red line). The green line is the system clock divided by 1, 2. 4 or 8. By default the system clock is divided by 1 and is at 32MHz :
cm_sys_clk_init(sysclk_XTAL32M);
cm_apb_set_clock_divider（apb_div1）;
cm_ahb_set_clock_divider(ahb_div1);
The red line is the output of the DivN HW block, and the frequency is always at 32Mhz regardless the aforementioned division.
The CLK_COM_REG handles the selection between the “green” and “red” line. The Low Level Drivers (LLD) are implemented with the 32MHz clock (red line) divN_clk. The clock frequency can be divided in the peripheral HW blocks further ( if it is possible).
Specifically for the SPI peripheral block, the clock speeds up to 32 MHz for the SPI controller and the SPI source clock can be divided by 2, 4, 8, 14 (according to datasheet). So the minimum SPI clock is at 32MHz / 14.
In case you want to lower down the SPI clock further, you should select the div1 for the peripheral clock and then lower down the System Clock to be able to get lower peripheral frequencies. This is not recommended, as the overall CPU performance will be lower. Additionally, in case of an event which will trigger in your app the change of a higher frequency to the system clock, for example plug in of the USB which require the PLL96, this will result to an unconditional change of the speed in your peripheral. You will have to take extra care in your application, so there will be absolutely no system clock changes during the transaction of your peripheral while using the divN.
If you still need to use 1MHz SPI clock, a possible workaround might be the following :
cm_sys_clk_init(sysclk_XTAL32M);
cm_apb_set_clock_divider(apb_div4);
cm_ahb_set_clock_divider（ahb_div4）;
新系统时钟将是32MHz / 4 = 8MHz
Thanks, PM_Dialog
Dear support
谢谢你的详细的回答。我检查这个workaround. It means
1.设置HCLK和PCLK分频器
cm_sys_clk_init(sysclk_XTAL32M);
cm_apb_set_clock_divider(apb_div4);
cm_ahb_set_clock_divider（ahb_div4）;
cm_lp_clk_init（）;
2. Modify hw_spi_init_clk_reg() function (I use SPI1)
void hw_spi_init_clk_reg（hw_spi_id ID）
{
ASSERT_WARNING(REG_GETF(CRG_TOP, PMU_CTRL_REG, COM_SLEEP) == 0);
if（id == hw_spi1）{
crg_com-> reset_clk_com_reg = crg_com_reset_clk_com_reg_spi_clk_sel_msk;
CRG_COM->SET_CLK_COM_REG = (CRG_COM_SET_CLK_COM_REG_SPI_ENABLE_Msk |CRG_COM_SET_CLK_COM_REG_SPI_CLK_SEL_Msk);
}else {
CRG_COM->RESET_CLK_COM_REG = CRG_COM_RESET_CLK_COM_REG_SPI2_CLK_SEL_Msk;
CRG_COM-> SET_CLK_COM_REG = CRG_COM_SET_CLK_COM_REG_SPI2_ENABLE_MSK;
}
}
3. divide SPI clock (with 14 -> 500k SCLK)
/* External sensor/module SPI driver */
const ad_spi_driver_conf_t drv_spi1_adis = {
.spi = {
.cs_pad = {DEVICE_CS_GPIO_PORT, DEVICE_CS_GPIO_PIN},
.word_mode = hw_spi_word_8bit，//在这里您可以定义所需的
.smn_role = HW_SPI_MODE_MASTER,
.polarity_mode = hw_spi_pol_low，//在这里您可以定义所需的SPI极性
.phase_mode = hw_spi_pha_mode_0，//在这里您可以在此处定义所需的SPI阶段
.mint_mode = hw_spi_mint_disable，
.xtal_freq = hw_spi_freq_div_14，
.fifo_mode = hw_spi_fifo_rx_tx，
.disabled = 0，/ *应在初始化阶段期间禁用* /
.ignore_cs = false,
.use_dma = true，
.rx_dma_channel = hw_dma_channel_2，
.tx_dma_channel = hw_dma_channel_4.
}
};
The result is unfortunately the same.
我再次检查了数据表，但对我来说不清楚你为什么写了，绿线是系统时钟除以1,2或8“。绿线是系统时钟。AHB和APB总线时钟是系统时钟除以1,2,4,8.绿线来自Sys_Clk选择器，直接来自XTAL32，RC32，PLL，LP时钟。我可以修改AHB和APB总线时钟，但随着我看到SPI外围时钟独立于AHB或APB总线时钟。（图84：SPI块图）。这些总线仅参加数据移动。
提前致谢
嗨Herangli，
I meant that if the ahb and apb bus clocks are divided, then the system clock is divided by 1,2,4,8 too. Please let me check it in my side and I’ll let you know.
我可以问你使用的SPI接口是什么，需要的SPI疏通速度小于1MHz吗？
谢谢pm_dialog.
Dear support
感谢您在您身边查看此问题。
当然，我想用ADIS16460进行高精度的IMU测量，并通过蓝牙发送测量。
这是ADIS传感器的数据表https://www.analog.com/en/products/adis16460.html
在数据表中，您可以在第5页顶部看到最大SPI时钟频率。
（我想在这篇文章之后我们可能会从模拟设备上询问一些钱，如广告成本:)）
提前致谢
Dear support
Did you have a chance to check this issue in an eval board?
先感谢您
Dear support
Did you have a chance to check this issue in an eval board?
先感谢您
嗨Herangli，
Thanks for the reminder and my apologies for the late response. I’ll give a try again.
Thanks, PM_Dialog
嗨Herangli，
Would it be possible to attach your project here to take a look?
Thanks, PM_Dialog