Setting SPI Clock Frequency

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BarryReinhold
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Setting SPI Clock Frequency

The CLK_PER_REG register (0x50000004) has the SPI_DIV field. The SPI_CTRL_REG has SPI_CLK field. The settings in SPI_CLK use the CLK_PER_REG settings.

What exactly do these two registers control? Is there more description on these outside of what is in DA14580_DS_v1.63.pdf?

On the SPI Master:
Is setting SPI_DIV to 0x2 (divide by 4) and SPI_CLK to 0x2 (XTAL)/(CLK_PER_REG*2) different from
setting SPI_DIV to 0x1 (divide by 2) and SPI_CLK to 0x1 (XTAL)/(CLK_PER_REG*4)?

On the SPI slave:
Does setting SPI_CLK have any impact in terms of how the slave samples arriving SPI data?

As a system:
Does SPI_DIV need to be set on the slave to match the value used by the master's SPI_DIV/SPI_CLK field? That is, if the master uses the above settings would the SPI slave need to set SPI_DIV to 0x3 (divide by 8)?

TR_Dialog
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Hi,

Hi,

Here are some information:

SPI_DIV in CLK_PER_REG takes effect first. The output of this "spi_clk" is further divided by 2, 4, 8 or 14 as defined by SPI_CTRL_REG[SPI_CLK].

In slave mode spi_clk, as defined above, should be at least 4x the clock frequency provided by the external SPI Master. This is required for proper sampling of the data line.

Thanks,

TR_DIALOG

BarryReinhold
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So are you saying that SPI

So are you saying that SPI_DIV in CLK_PER_REG controls the SPI sampling rate, and that he SPI clock signaling rate is further refined by SPI_CLK in SPI_CTRL_REG?
So my most robust setting would be SPI_DIV set to 0x03, and SPI_CLK set to 0x11 (16mhz/8) = 2mhz sampling with SPI_CLK at 14.2khz?

Is it correct to assume that SPI_DIV applies to the sampling rate of the SPI block on the SPI master too (if using the DA14580 as SPI master)?

TR_Dialog
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In both Master and Slave

In both Master and Slave Modes, "spi_clk" is controlled by SPI_DIV in CLK_PER_REG. You have referred to that as SPI sampling rate above.
Setting SPI_DIV to 0x3 will result in "spi_clk" of 2 Mhz.

"spi_clk" is further divided as per setting of SPI_CLK in SPI_CTRL_REG.
0x11 is not a valid value for SPI_CLK in SPI_CTRL_REG.
If you meant setting SPI_CLK bits to 0x03, it will result in SPI clock frequency of (2 MHz/ 14).
Not sure, what you mean by "robust setting".