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DA14580 Development Kit - Basic

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TheDA14585 and DA14586are available for new designs.

DA14580 Board – Basic

Get ahead of the competition

This DA14580 basic development kit gives you all flexibility to develop with confidence. All of the DA14580’s I/Os are available and mapped on to expansion connectors. A debugger is provided on the PCB which in combination with SmartSnippets™, Dialog’s complete software environment, enables you to program and test your applicatiions.

SmartBond™:power, size and system cost without compromise

Features

All flexibility

All I/O’s available and mapped on to expansion connectors

Onboard debugger

Complete software environment available

Starter kit

Board

Battery

USB cable

Quick starting guide

DA14580 Development Kit - Pro

Product Briefs and Summaries
Name Date Version
SmartBond™ DA1458x Family Product Brief(2.82 MB) 22/06/2017 1.0
Datasheets
Name Date Version
DA14580 Datasheet(2.64 MB) 09/11/2016 3.4
Application notes
Name Date Version
AN-B-052 DA145Xx/68x Development Kit J-Link Interface(492.82 KB) 14/02/2017 1.0
Design tools
Name Date Version
DA14580 DEVKT -Basic: Electrical Schematic, BOM-, Layout-, Design- and Gerber-files(1.64 MB) 08/10/2018 2.3
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SmartBond™ DA14580 - Development Kit - Basic

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3年go

DSPS Minor Modification

Posted bychanmi1680 points 3 replies
0 upvotes

Hi,

I am following the DSPS project and have some success. I made a mistake in my PCB such, but I think it's possible to fix it by swapping the UART ports. Is it ok to swap UART1 ports with UART2 ports? In other words, line 45-69 in user_periph_setup.h becomes:

/****************************************************************************************/
/* UART configuration */
/****************************************************************************************/

#define GPIO_UART1_TX_PORT GPIO_PORT_1
#define GPIO_UART1_TX_PIN GPIO_PIN_3
#define GPIO_UART1_RX_PORT GPIO_PORT_1
#define GPIO_UART1_RX_PIN GPIO_PIN_2
#define GPIO_UART1_RTS_PORT GPIO_PORT_0
#define GPIO_UART1_RTS_PIN GPIO_PIN_3
#define GPIO_UART1_CTS_PORT GPIO_PORT_0
#define GPIO_UART1_CTS_PIN GPIO_PIN_2

/****************************************************************************************/
/* UART2 GPIO configuration */
/****************************************************************************************/

#ifdef CFG_PRINTF_UART2
#define GPIO_UART2_TX_PORT GPIO_PORT_0
#define GPIO_UART2_TX_PIN GPIO_PIN_4

#define GPIO_UART2_RX_PORT GPIO_PORT_0
#define GPIO_UART2_RX_PIN GPIO_PIN_5
#endif
/*

Thanks in advance for your help.

Regards,
Michael

3年go

woshobruuefrip… 0 points

Hi chanmi168,

Your configuration is proper, but only for the CSP packages, in the cases of QFN40 andQFN48 the specified pins it is not recommended to be toggled (Please check the AN-B009.pdf).You will be able to find the document in the Application Notes section at the documents tab.

Thanks,

STS_Dialog.

3年go

chanmi168 0 points

Hi,

It seems like P1_2 and P1_3 cannot (instead of not recommended) be toggle when 16MHz XTAL active (p5). Based on your experience, should I not even bother to try or there is still a chance? Thanks for guiding me to the right document, that was useful.

Thanks,
Michael

3年go

woshobruuefrip… 0 points

Hi,

Only for the CSP packages, you can have the configuration that you mentioned ,in other case there will be problem.

Thanks,

STS_Dialog