Designers prefer to design in flexibility. The reasons are legion and mostly obvious: you may not know today how a chip will be used tomorrow – best to delay setting anything in concrete until you are sure how it is going to be used. You may not fully understand the design until it is nearing completion, and premature optimization can leave you in a difficult situation. And there are more practical considerations – getting buy-in from stakeholders on a set of restrictive requirements can be very difficult. Allowing the hard decisions to be shelved for later is almost always the easier option.

因此，这种方法通常是增加更多的灵活性而不是更少。这意味着允许通过软件配置系统，并且在近时允许硬件本身直接配置嵌入的可编程资源（嵌入式FPGA块等）。

But there are other pressures in designing any chip and living as we now do in a post-Moore world, some of those are becoming more prominent.

随着过程之间的越来越多的时间缩小和这些新技术的成本上升，增加了我们已经拥有的技术的更多信息。对于一些，使用成本降低并随着时间的推移增加能力增加的架子组件的策略现在看起来有缺陷。这些设计人员现在正在寻找定制芯片，让他们继续通过定制解决方案继续节省成本并提高功能，这些解决方案可以紧密地架构以解决特定问题。在构建某些解决方案的一些灵活性时可能是一个好主意，一般来说，如果问题空间是众所周知的，可以制作一个芯片，以解决这种需求，而不会浪费资源以额外的灵活性。

在最终解决方案中，人们还需要在芯片的灵活部件方面涉及的成本。这些团队通常位于最终用户组织中，而芯片在其他地方设计，因此现在这些团队必须了解并开发他们未参与设计的芯片的代码。这意味着时间和金钱将花费这些团队在芯片设计的细节上速度。

完全是，这是大量潜在的成本 - 到设计师和最终用户 - 只是为了使用芯片的灵活性来定制解决方案，当可能已经决定并从一开始就可以进入设计。

Of course, some designs demand a lot of flexibility, for example, to support a new standard. The standard you are working towards may still be in flux, but you want to be first to market. Therefore, you may want to have some of the details that are not yet agreed on kept in an FPGA where they can be changed after the chip is manufactured. There is a cost associated with this of course, but this is likely offset by meeting your market window.

嵌入在SOC中的处理器一直是尖食，因为它具有比尝试直接在硬件中直接复制复杂逻辑的更具成本效益，特别是当要运行的软件可能需要在以后更改时。同样，您需要特定的问题，您需要专用硬件，但该硬件要求将改变。在这种情况下，允许重新配置的硬件可以节省硅区域并导致更优雅的设计。但是，这些用例，虽然重要，但一般都会更少 - 大多数芯片都不需要那种重新配置水平。

相反，所需要的是在理解芯片正在设计和使芯片的艰难决策中的问题空间进行了解到，这是芯片且不会做的问题。通过提前执行此操作，您可以拥有更便宜的芯片，即可与最终用户的最少工作一起使用。结果是您可以更快地上市，具有较便宜的产品。

In times past, adding more technology could help delay difficult decisions. In a post-Moore world, better engineering and better architectures are the road to success. At Adesto, we like to take a holistic view of the discovery process in ASIC definitions so this will include the chips requirements but also any potential future proofing that can be allowed for. Learn more about our ASICs这里今天。