6 Internal Blocks Configuration
6.1 OpAmp0 and OpAmp1 Configurations
OpAmp configurations are shown in Figure 4.
Figure 4: Operational Amplifier 0, 1 Settings
6.2 Chopper ACMP Configuration
Chopper ACMP configuration is shown in Figure 5.
Figure 5: Chopper ACMP Settings
6.3 HD Buffer Configuration
HD Buffer shares the internal voltage reference with OpAmp0 macrocell. Note that in the current project internal Vref is disconnected from the OpAmp0. The power-up source for HD Buffer is the connection matrix signal. The HD Buffer and OpAmp0 Vref configurations are shown in Figure 6.
Figure 6: HD Buffer and OpAmp0 Vref Settings
6.4 ACMP Buffer Configuration
To use ACMP buffer as a voltage follower, the ACMP1 and Vref1 macrocells should be configured as shown in Figure 7:
Figure 7: ACMP1L and Vref1 Settings
6.5 Oscillators Configurations
Oscillator1 uses default settings. Oscillator0 configuration is shown in Figure 8.
Figure 8: Oscillator0 Settings
6.6 Delay Macrocells Configurations
Delay configurations are shown in Figure 9.
Figure 9: Delay Macrocells Settings
6.7 P DLY Configuration
P DLY configuration is shown in Figure 10.
6.8 LUTs Configurations
LUTs configurations are shown in Figure 11.
6.8 Digital Rheostat 0 Configuration
Digital Rheostat 0 configuration is shown in Figure 12.
Figure 12: Digital Rheostat 0 Settings
6.10 Analog Switch 1 Configuration
Analog Switch 1 configuration is shown in Figure 13.
Figure 13: Analog Switch 1 Settings
6.11 I²C Macrocell Configuration
I²C macrocell uses default configurations.
6.12 GPIOs Configurations
GPIOs configurations are shown in Figure 14.
