6 PISO Shift Register

庇索移位寄存器the converse of the SIPO shift register. The inputs are presented simultaneously in parallel, and the output is retrieved serially. The data is taken out one bit per clock cycle. The main point to note in this shift register is that a clock is not required to load the data in the shift register, whereas a clock is required to unload the data.

Similar to the other shift registers, all the DFF's are clocked by the same clock and have the nReset set high for normal operation. 2-bit lookup tables provided in the IC are used as OR gates to provide parallel input to the DFF's as well as transmit the output of one DFF as the input to the next DFF. The output is retrieved serially from the output of DFF10.

Figure 5: 8-bit Parallel In Serial Out Shift Register

This type of shift register is typically used for data conversion from parallel to serial. All the parallel bits with the data are serially transmitted to the single input of a microprocessor which helps in using fewer input pins of the microprocessor.

The timing diagram shown in Fig. 6 depicts the clock and all parallel inputs, highlighted between two vertical orange lines. The last waveform is the serial data out which shows how all the parallel inputs are converted into a serial bitstream.

The way how inputs correspond to output is shown below.

Figure 6: Timing Diagram of 8-bit Parallel In Serial Out Shift Register