5 SIPO Shift Register

In this type of shift register, the data is sent serially and retrieved in parallel. All the DFF's are clocked by the same clock and nReset is used to ensure that all the DFF's are enabled for normal operation. The data is fed serially into DFF3. All the parallel outputs are from the outputs of the DFF that are present in the shift register. The output of each intermediate DFF is fed as input to the next DFF. All 8 input serial bits will be available at the parallel outputs after 8 rising edges of the clock.

Figure 3: 8-bit Serial In Parallel Out Shift Register

The timing diagram of the SIPO shift register is shown in Fig 4. It has a clock and Serial Data-in as the first two waveforms, and all other waveforms are the outputs of the DFF's. It can be observed that after the 8th rising edge of the clock, the entire input data bits are visible at the output of each DFF.

The first bit which is transmitted serially is observed at the last DFF's output. The main application of the SIPO shift register is data conversion in many digital applications. Sometimes the SIPO shift register is connected to the output of a microprocessor when more GPIO pins are required. In the above design, the clock frequency is 1 kHz and the time taken to convert the 8 serial bits to parallel bits is 8 ms.

The correspondence between input to output is shown below:

Figure 4: Timing Diagram of 8-bit Serial In Parallel Out Shift Register