1 year ago
What is the maximum clock speed for SWD supported by DA14695?
Posted byPeter Luo0 points 6 repliesHi Dialog,
What is the maximum clock speed for SWD supported by DA14695?
The maximum clock speed of segger JLink-OB is 2666kHz, the testrspeed result is 185 KByte/sec, it is too slow for us.
可以采用30 mhz目标interface speed to access DA14695 through external ultra fast debug probe such as Segger J-Link ULTRA+?
BR/Peter
C:\Program Files (x86)\SEGGER\JLink_V662a>jlink -device DA14695 -speed 4000 -si swd SEGGER J-Link Commander V6.62a (Compiled Jan 31 2020 12:58:42) DLL version V6.62a, compiled Jan 31 2020 12:58:08 Connecting to J-Link via USB...O.K. Firmware: J-Link OB-SAM3U128 V3 compiled Jan 21 2020 17:31:29 Hardware version: V3.00 S/N: 483050749 VTref=3.300V Type "connect" to establish a target connection, '?' for help J-Link>connect Device "DA14695" selected. Connecting to target via SWD Found SW-DP with ID 0x0BE12477 DPIDR: 0x0BE12477 Scanning AP map to find all available APs AP[1]: Stopped AP scan as end of AP map has been reached AP[0]: AHB-AP (IDR: 0x14770015) Iterating through AP map to find AHB-AP to use AP[0]: Core found AP[0]: AHB-AP ROM base: 0xE00FF000 CPUID register: 0x410FD212. Implementer code: 0x41 (ARM) Found Cortex-M33 r0p2, Little endian. FPUnit: 8 code (BP) slots and 0 literal slots Security extension: not implemented CoreSight components: ROMTbl[0] @ E00FF000 ROMTbl[0][0]: E000E000, CID: B105900D, PID: 000BBD21 Cortex-M33 ROMTbl[0][1]: E0001000, CID: B105900D, PID: 000BBD21 DWT ROMTbl[0][2]: E0002000, CID: B105900D, PID: 000BBD21 FPB ROMTbl[0][6]: E0042000, CID: B105900D, PID: 000BBD21 CTI ROMTbl[0][7]: E0043000, CID: B105900D, PID: 000BBD21 MTB Cortex-M33 identified. J-Link>st VTref=3.300V ITarget=0mA TCK=0 TDI=1 TDO=1 TMS=1 TRES=1 TRST=1 Supported target interface speeds: - 16 MHz/n, (n>=6). => 2666kHz, 2285kHz, 2000kHz, ... - Adaptive clocking J-Link>testrspeed Speed test: Reading 8 * 128kb from address 0x00000000 ........ 128 kByte read in 705ms ! (185 KByte/sec) J-Link>1 year ago
Hi Dialog,
We are using the DA1469X USB Development Kit, the debug interface should be JLink Lite too. Our fast debug probe is not in my hand now, so can't do test now. I want to know if DA1469X chip has capablity to support more higher speed than 2666kHz?
Thanks, Peter
1 year ago
Hi Peter Luo,
This is not a limitation on the DA149x. The max SWD signals that it can be generated by the J-Link Lite is 2666KHz. You can test in your side as well. You can open the GDB Server, set the SWD clock to 50000KHz and you will see that again the clock is around 2666KHz. If you would like to increase the SWD clock speed, then you should use another debugger.
Thanks, PM_Dialog
1 year ago
Hi Dialog,
Very happy to hear no limitation on the DA149x !
We'll use the double debug interfaces as output data channels for GPADC in our new design.
Thank you so much!
BR/Peter
1 year ago
Hi Peter,
You also refer to DA1469x datasheet. Can you please provide further details on what you are planning to accomplish with the double debug interfaces as output data channels for GPAD? Is the SWD clock speed important?
Thanks, PM_Dialog
1 year ago
Hi Dialog,
Yes. The SWD clock speed is very important for us. We want to use DA1469x to convert an analog signal to digital data stream at maximum sampling rate 4 Msample/s, and upload data to host as fast as possible. If only USB interface be used, the speed is just about 900kB/s, so we want use debug interfaces to speedup.
Finally, the two debug probes will be replaced with one FTDICHIP FT4232H chip or others with our SWD software.
Thanks, Peter
1 year ago
Hi Peter Luo,
Thanks for your query. Which version of JLink are you using? In our Development Boards, we are using the JLink Lite and the maximum SWD clock speed is up to 2666kHz.
Thanks, PM_Dialog